ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.295 VCVT, VCVTR (between floating-point and integer, VFP)
These instructions convert a value in a register from floating-point to a 32-bit integer, or from a 32-bit integer
to floating-point, and place the result in a second register.
The floating-point to integer operation normally uses the Round towards Zero rounding mode, but can
optionally use the rounding mode specified by the FPSCR. The integer to floating-point operation uses the
rounding mode specified by the FPSCR.
VCVT (between floating-point and fixed-point, VFP) on page A8-582 describes conversions between
floating-point and 16-bit integers.
Encoding T1 / A1 VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)
VCVT{R}.S32.F64 ,
VCVT{R}.S32.F32 ,
VCVT{R}.U32.F64 ,
VCVT{R}.U32.F32 ,
VCVT.F64. ,
VCVT.F32. ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 0 1 D 1 1 1 opc2 Vd 1 0 1 sz op 1 M 0 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 1 0 1 D 1 1 1 opc2 Vd 1 0 1 sz op 1 M 0 Vm
if opc2 != ‘000’ && opc2 != ‘10x’ then SEE “Related encodings”;
to_integer = (opc2 == ‘1’); dp_operation = (sz == 1);
if to_integer then
unsigned = (opc2 == ‘0’); round_zero = (op == ‘1’);
d = UInt(Vd:D); m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
else
unsigned = (op == ‘0’); round_fpscr = FALSE; // FALSE selects FPSCR rounding
m = UInt(Vm:M); d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
Related encodings See VFP data-processing instructions on page A7-24
A8-578 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B