ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug State
C5.5.2 Altering CPSR privileged bits in Debug state
On processors that implement the Security Extensions, the processor:
prevents attempts to set the CPSR.M field to a value that would place the processor in a mode or
security state where debug is not permitted
prevents updates to the Privileged bits of the CPSR in cases where Secure User halting debug is
supported, the processor is in Secure User mode, and invasive debug is not permitted in Secure
privileged modes
prevents attempts to set the CPSR.M field to 0b10001, FIQ mode, if NSACR.RFR == 1 and the
processor is in Non-secure state.
On processors that do not implement the Security Extensions, all CPSR updates that are permitted in a
privileged mode when in Non-debug state, are permitted in Debug state.
Table C5-4 defines the behavior on writes to the CPSR in Debug state.
Mode Secure state
Logical
(DBGEN AND
SPIDEN)
Table C5-4 Permitted updates to the CPSR in Debug state
SU halting
debug a
supported
Update privileged
CPSR bits b
Modify CPSR.M to
Monitor mode
User Yes 0 Yes Update ignored UNPREDICTABLE c
No Permitted d Permitted
Privileged Yes 0 X Permitted d Permitted
Any No 0 X Permitted d UNPREDICTABLE e
Any X 1 X Permitted d Permitted
a. Secure User halting debug support.
b. This column does not apply to changing CPSR.M to Monitor mode. Apart from this, the CPSR bits are defined in
Program Status Registers (PSRs) on page B1-14, and this column does apply to changing CPSR.M to any other value.
c. The definition of UNPREDICTABLE implies the processor must not enter a privileged mode.
d. Except that, regardless of the state of SPIDEN:
The SCR.AW, SCR.FW and SCTLR.NMFI bits have the same effects on writes to CPSR.A and CPSR.F as they do
in Non-debug state, see Control of exception handling by the Security Extensions on page B1-41 and
Non-maskable fast interrupts on page B1-18.
The NSACR.RFR bit has the same effect on writes to CPSR.M as it does in Non-debug state, see
c1, Non-Secure Access Control Register (NSACR) on page B3-110.
e. The definition of UNPREDICTABLE implies the processor must not enter Monitor mode, and must not enter FIQ mode
when NSACR.RFR == 1.
C5-14 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B