ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
The SP can be in the list in ARM code, but not in Thumb code. However, ARM instructions
that include the SP in the list are deprecated.
The PC can be in the list. If it is, the instruction branches to the address loaded to the PC. In
ARMv5T and above, this is an interworking branch, see Pseudocode details of operations
on ARM core registers on page A2-12. In Thumb code, if the PC is in the list:
the LR must not be in the list
the instruction must be either outside any IT block, or the last instruction in an IT
block.
ARM instructions that include both the LR and the PC in the list are deprecated.
Instructions with the base register in the list and ! specified are only available in the ARM
instruction set before ARMv7, and the use of such instructions is deprecated. The value of
the base register after such an instruction is UNKNOWN.
LDMEA is a pseudo-instruction for LDMDB, referring to its use for popping data from Empty Ascending stacks.
The pre-UAL syntaxes LDMDB and LDMEA are equivalent to LDMDB.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); NullCheckIfThumbEE(n);
address = R[n] - 4*BitCount(registers);
for i = 0 to 14
if registers == ‘1’ then
R[i] = MemA[address,4]; address = address + 4;
if registers == ‘1’ then
LoadWritePC(MemA[address,4]);
if wback && registers == ‘0’ then R[n] = R[n] - 4*BitCount(registers);
if wback && registers == ‘1’ then R[n] = bits(32) UNKNOWN;
Exceptions
Data Abort.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-115