ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Instruction Set Encoding
A5.2 Data-processing and miscellaneous instructions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 op op1 op2
Table A5-2 shows the allocation of encodings in this space.
Table A5-2 Data-processing and miscellaneous instructions
op op1 op2 Instruction or instruction class Variant
0 not 10xx0 xxx0 Data-processing (register) on page A5-5 -
0xx1 Data-processing (register-shifted register) on page A5-7 -
10xx0 0xxx Miscellaneous instructions on page A5-18 -
1xx0 Halfword multiply and multiply-accumulate on page A5-13 -
0xxxx 1001 Multiply and multiply-accumulate on page A5-12 -
1xxxx 1001 Synchronization primitives on page A5-16 -
not 0xx1x 1011 Extra load/store instructions on page A5-14 -
11x1 Extra load/store instructions on page A5-14 -
0xx1x 1011 Extra load/store instructions (unprivileged) on page A5-15 -
11x1 Extra load/store instructions (unprivileged) on page A5-15 -
1 not 10xx0 - Data-processing (immediate) on page A5-8 -
10000 - 16-bit immediate load (MOV (immediate) on page A8-194) v6T2
10100 - High halfword 16-bit immediate load (MOVT on page A8-200) v6T2
10x10 - MSR (immediate), and hints on page A5-17 -
A5-4 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B