ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Thumb Instruction Set Encoding
A6.3.18 Coprocessor instructions
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 op1 Rn coproc op
Table A6-29 shows the allocation of encodings in this space. These encodings are all available in ARMv6T2
and above.
op1 op coproc Rn Instructions See
000x1x
001xxx
01xxxx
000x10
001xx0
01xxx0
000x11
001xx1
01xxx1
000x11
001xx1
01xxx1
Table A6-29 Coprocessor instructions
- 101x - Advanced SIMD, VFP Extension register load/store
instructions on page A7-26
- not 101x - Store Coprocessor STC, STC2 on page A8-372
- not 101x not 1111 Load Coprocessor (immediate) LDC, LDC2 (immediate) on
page A8-106
- not 101x 1111 Load Coprocessor (literal) LDC, LDC2 (literal) on page A8-108
00000x - - - UNDEFINED -
00010x - 101x - Advanced SIMD, VFP 64-bit transfers between ARM core
and extension registers on page A7-32
000100 - not 101x - Move to Coprocessor from two
ARM core registers
000101 - not 101x - Move to two ARM core
registers from Coprocessor
MCRR, MCRR2 on page A8-188
MRRC, MRRC2 on page A8-204
10xxxx 0 101x - VFP VFP data-processing instructions on
page A7-24
not 101x - Coprocessor data operations CDP, CDP2 on page A8-68
A6-40 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B