ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B3.12.6 CP15 c0, ID codes registers
Virtual Memory System Architecture (VMSA)
The CP15 c0 registers are used for processor and feature identification. Figure B3-11 shows the CP15 c0
registers.
CRn opc1 CRm opc2
c0 0 c0
0
MIDR, Main ID Register
1
CTR, Cache Type Register
2
TCMTR, TCM Type Register, details IMPLEMENTATION DEFINED
3
TLBTR, TLB Type Register, details IMPLEMENTATION DEFINED
5
MPIDR, Multiprocessor Affinity Register
{4,6,7} Aliases of Main ID Register
c1 0
‡ ID_PFR0, Processor Feature Register 0
1
‡ ID_PFR1, Processor Feature Register 1
2
‡ ID_DFR0, Debug Feature Register 0
3
‡ ID_AFR0, Auxiliary Feature Register 0
4
‡ ID_MMFR0, Memory Model Feature Register 0
5
‡ ID_MMFR1, Memory Model Feature Register 1
6
‡ ID_MMFR2, Memory Model Feature Register 2
7
‡ ID_MMFR3, Memory Model Feature Register 3
c2
0
‡ ID_ISAR0, ISA Feature Register 0
1
‡ ID_ISAR1, ISA Feature Register 1
2
‡ ID_ISAR1, ISA Feature Register 2
3
‡ ID_ISAR1, ISA Feature Register 3
4
‡ ID_ISAR4, ISA Feature Register 4
5
‡ ID_ISAR5, ISA Feature Register 5
{6,7} Read-As-Zero
{c3-c7} {0-7} Read-As-Zero
1
c0
0
CCSIDR, Cache Size ID Registers
1
CLIDR, Cache Level ID Register
7
AIDR, Auxiliary ID Register IMPLEMENTATION DEFINED
2
c0
0
CSSELR, Cache Size Selection Register
Read-only Read/Write
Write-only
‡ CPUID registers
Figure B3-11 CP15 c0 registers in a VMSA implementation
CP15 c0 register encodings not shown in Figure B3-11 are UNPREDICTABLE, see Unallocated CP15
encodings on page B3-69.
Note
Chapter B5 The CPUID Identification Scheme describes the CPUID registers shown in Figure B3-11.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-79