ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.318 VLD4 (single 4-element structure to all lanes)
This instruction loads one 4-element structure from memory into all lanes of four registers. For details of
the addressing mode see Advanced SIMD addressing mode on page A7-30.
Encoding T1 / A1 Advanced SIMD
VLD4. , [{ @}]{!}
VLD4. , [{ @}],
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 1 D 1 0 Rn Vd 1 1 1 1 size T a Rm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd 1 1 1 1 size T a Rm
if size == ‘11’ && a == ‘0’ then UNDEFINED;
if size == ‘11’ then
ebytes = 4; elements = 2; alignment = 16;
else
ebytes = 1 31 then UNPREDICTABLE;
Assembler syntax
VLD4. , [{ @}] Rm = ’1111’
VLD4. , [{ @}]! Rm = ’1101’
VLD4. , [{ @}], Rm = other values
where:
See Standard assembler syntax fields on page A8-7. An ARM VLD4 instruction must be
unconditional.
The data size. It must be one of:
8 encoded as size = 0b00
16 encoded as size = 0b01
32 encoded as size = 0b10 (or 0b11 for 16-byte alignment).
The registers containing the structures. It must be one of:
{, , , }
single-spaced registers, encoded as D:Vd = , T = 0
A8-624 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B