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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Bn, bit [n], for n = 0 to 7<br />

Bufferability bit, B, for memory protection region n.<br />

Accessing the Memory Region Bufferability Register<br />

<strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5 Differences<br />

To access the Memory Region Bufferability Register you read or write the CP15 registers with set to<br />

0, set to c3, set to c0, <strong>and</strong> set to 0. For example:<br />

MRC p15,0,,c3,c0,0 ; Read CP15 Data or unified Region Bufferability Register<br />

MCR p15,0,,c3,c0,0 ; Write CP15 Data or unified Region Bufferability Register<br />

c5, Memory Region Access Permissions Registers (DAPR <strong>and</strong> IAPR)<br />

The two Memory Region Access Permissions Registers are:<br />

The Data or unified Access Permissions Register, DAPR.<br />

The Instruction Access Permissions Register, IAPR. The IAPR is implemented only when the<br />

processor implements separate data <strong>and</strong> instruction memory protection region definitions.<br />

A Memory Region Access Permissions Register hold the access permission bits AP[1:0] for each of the<br />

eight memory protection regions.<br />

The format of a Memory Region Access Permissions Register is:<br />

31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Reserved AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0<br />

Bits [31:16] Reserved. UNK/SBZP.<br />

APn, bits [2n+1:2n], for n = 0 to 7<br />

Access permission bits AP[1:0] for memory protection region n.<br />

For details of the significance <strong>and</strong> encoding of these bits see Table H-10 on page AppxH-29.<br />

If the implementation does not permit the requested type of access, it signals an abort to the processor.<br />

Accessing the Memory Region Access Permissions Registers<br />

To access the Memory Region Access Permissions Registers you read or write the CP15 registers with<br />

set to 0, set to c5, set to c0, <strong>and</strong> set as follows:<br />

0 if there is only a single set of protection regions<br />

when there are separate memory protection regions for data <strong>and</strong> instructions:<br />

— 0 to access the Data Region Access Permissions Register<br />

— 1 to access the Instruction Region Access Permissions Register.<br />

For example:<br />

MRC p15,0,,c5,c0,0 ; Read CP15 Data or unified Region Access Permissions Register<br />

MCR p15,0,,c5,c0,0 ; Write CP15 Data or unified Region Access Permissions Register<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. AppxH-45

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