ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
SBC{S} {,} , ,
where:
Instruction Details
S If S is present, the instruction updates the flags. Otherwise, the flags are not updated.
See Standard assembler syntax fields on page A8-7.
The destination register.
The first operand register.
The register that is shifted and used as the second operand.
The type of shift to apply to the value read from . It must be one of:
ASR Arithmetic shift right, encoded as type = 0b10
LSL Logical shift left, encoded as type = 0b00
LSR Logical shift right, encoded as type = 0b01
ROR Rotate right, encoded as type = 0b11.
The register whose bottom byte contains the amount to shift by.
The pre-UAL syntax SBCS is equivalent to SBCS.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
shift_n = UInt(R[s]);
shifted = Shift(R[m], shift_t, shift_n, APSR.C);
(result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), APSR.C);
R[d] = result;
if setflags then
APSR.N = result;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
APSR.V = overflow;
Exceptions
None.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-307