ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
The registers containing the structure. Encoded with D:Vd = . It must be one of:
{, } Single-spaced registers, see Table A8-6.
{, } Double-spaced registers, see Table A8-6.
This is not available if == 8.
Contains the base address for the access.
The alignment. It can be one of:
16 2-byte alignment, available only if is 8
32 4-byte alignment, available only if is 16
64 8-byte alignment, available only if is 32
omitted Standard alignment, see Unaligned data access on page A3-5.
! If present, specifies writeback.
Contains an address offset applied after the access.
For more information about , !, and see Advanced SIMD addressing mode on page A7-30.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
if wback then R[n] = R[n] + (if register_index then R[m] else 2*ebytes);
Elem[D[d],index,esize] = MemU[address,ebytes];
Elem[D[d2],index,esize] = MemU[address+ebytes,ebytes];
Exceptions
Undefined Instruction, Data Abort.
Table A8-6 Encoding of index, alignment, and register spacing
== 8 == 16 == 32
Index index_align[3:1] = x index_align[3:2] = x index_align[3] = x
Single-spacing - index_align[1] = 0 index_align[2] = 0
Double-spacing - index_align[1] = 1 index_align[2] = 1
omitted index_align[0] = 0 index_align[0] = 0 index_align[1:0] = ’00’
== 16 index_align[0] = 1 - -
== 32 - index_align[0] = 1 -
== 64 - - index_align[1:0] = ’01’
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-611