ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
Accessing the Cache Dirty Status Register
To access the Cache Dirty Status Register you read the CP15 registers with set to 0, set to c7,
set to c10, and set to 6. For example:
MRC p15, 0, , c7, c10, 6
Cleaning and invalidating operations for the entire data cache
The CP15 c7 encodings include operations for cleaning the entire data cache, and for performing a clean
and invalidate of the entire data cache. If these operations are interrupted, the LR value that is captured on
the interrupt is (address of instruction that launched the cache operation + 4). This permits the standard
return mechanism for interrupts to restart the operation.
If a particular operation requires that the cache is clean, or clean and invalid, then it is essential that the
sequence of instructions for cleaning or cleaning and invalidating the cache can cope with the arrival of an
interrupt at any time when interrupts are not disabled. This is because interrupts might write to a previously
cleaned cache block. For this reason, the Cache Dirty Status Register indicates whether the cache has been
written to since the last successful cache clean.
You can interrogate the Cache Dirty Status Register to determine whether the cache is clean, and if you do
this while interrupts are disabled, a subsequent operation can rely on having a clean cache. The following
sequence illustrates this approach.
; The following code assumes interrupts are enabled at this point.
Loop1
MOV R1, #0
MCR p15, 0, R1, c7, c10, 0 ; Clean data cache. For Clean and Invalidate,
; use MCR p15, 0, R1, c7, c14, 0 instead
MRS R2, CPSR ; Save PSR context
CPSID iaf ; Disable interrupts
MRC p15, 0, R1, c7, c10, 6 ; Read Cache Dirty Status Register
TST R1, #1 ; Check if it is clean
BEQ UseClean
MSR CPSR_xc, R2 ; Re-enable interrupts
B Loop1 ; Clean the cache again
UseClean
Do_Clean_Operations ; Perform whatever operation relies on
; the cache being clean or clean & invalid.
; To reduce impact on interrupt latency,
; this sequence should be short.
MCR p15, 0, R1, c7, c6, 0 ; Optional. Can use this Invalidate all command
; to invalidate a Clean loop.
MSR CPSR_xc, R2 ; Re-enable interrupts
Note
The long cache clean operation is performed with interrupts enabled throughout this routine.
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