ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
V.F32 {,} , Encoded as Q = 1
V.F32 {,} , Encoded as Q = 0
where:
Must be one of:
MAX encoded as op = 0
MIN encoded as op = 1.
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VMAX or VMIN
instruction must be unconditional.
, , The destination vector and the operand vectors, for a quadword operation.
, , The destination vector and the operand vectors, for a doubleword operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
op1 = Elem[D[n+r],e,esize]; op2 = Elem[D[m+r],e,esize];
Elem[D[d+r],e,esize] = if maximum then FPMax(op1,op2,FALSE) else FPMin(op1,op2,FALSE);
Exceptions
Undefined Instruction.
Floating-point maximum and minimum
max(+0.0, –0.0) = +0.0
min(+0.0, –0.0) = –0.0
If any input is a NaN, the corresponding result element is the default NaN.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-633