ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Pseudocode Definition
I.2 Limitations of pseudocode
The pseudocode descriptions of instruction functionality have a number of limitations. These are mainly due
to the fact that, for clarity and brevity, the pseudocode is a sequential and mostly deterministic language.
These limitations include:
Pseudocode does not describe the ordering requirements when an instruction generates multiple
memory accesses, except in the case of SWP and SWPB instructions where the two accesses are to the
same memory location. For a description of the ordering requirements on memory accesses see
Memory access order on page A3-41.
Pseudocode does not describe the exact rules when an UNDEFINED instruction fails its condition
check. In such cases, the UNDEFINED pseudocode statement lies inside the if ConditionPassed()
then ... structure, either directly or in the EncodingSpecificOperations() function call, and so the
pseudocode indicates that the instruction executes as a NOP. Conditional execution of undefined
instructions on page B1-51 describes the exact rules.
Pseudocode does not describe the exact ordering requirements when one VFP instruction generates
more than one floating-point exception. The exact rules are described in Combinations of exceptions
on page A2-44.
The pseudocode statements UNDEFINED, UNPREDICTABLE and SEE indicate behavior that differs from that
indicated by the pseudocode being executed. If one of them is encountered:
— Earlier behavior indicated by the pseudocode is only specified as occurring to the extent
required to determine that the statement is executed.
— No subsequent behavior indicated by the pseudocode occurs. This means that these statements
terminate pseudocode execution.
For more information, see Simple statements on page AppxI-17.
A processor exception can be taken during execution of the pseudocode for an instruction, either
explicitly as a result of the execution of a pseudocode function such as DataAbort(), or implicitly, for
example if an interrupt is taken during execution of an LDM instruction. If this happens, the pseudocode
does not describe the extent to which the normal behavior of the instruction occurs. To determine that,
see the descriptions of the processor exceptions in Exceptions on page B1-30.
AppxI-4 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B