ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.382 VSHL (immediate)
Vector Shift Left (immediate) takes each element in a vector of integers, left shifts them by an immediate
value, and places the results in the destination vector.
Bits shifted out of the left of each element are lost.
The elements must all be the same size, and can be 8-bit, 16-bit, 32-bit, or 64-bit integers. There is no
distinction between signed and unsigned integers.
Encoding T1 / A1 Advanced SIMD
VSHL.I , , #
VSHL.I , , #
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 1 1 D imm6 Vd 0 1 0 1 L Q M 1 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 0 1 D imm6 Vd 0 1 0 1 L Q M 1 Vm
if L:imm6 == ‘0000xxx’ then SEE “Related encodings”;
if Q == ‘1’ && (Vd == ‘1’ || Vm == ‘1’) then UNDEFINED;
case L:imm6 of
when ‘0001xxx’ esize = 8; elements = 8; shift_amount = UInt(imm6) - 8;
when ‘001xxxx’ esize = 16; elements = 4; shift_amount = UInt(imm6) - 16;
when ‘01xxxxx’ esize = 32; elements = 2; shift_amount = UInt(imm6) - 32;
when ‘1xxxxxx’ esize = 64; elements = 1; shift_amount = UInt(imm6);
d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == ‘0’ then 1 else 2;
Related encodings See One register and a modified immediate value on page A7-21
A8-750 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B