ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VLD1. , [{@}] Rm = ’1111’
VLD1. , [{@}]! Rm = ’1101’
VLD1. , [{@}], Rm = other values
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VLD1 instruction must be
unconditional.
The data size. It must be one of:
8 encoded as size = 0b00
16 encoded as size = 0b01
32 encoded as size = 0b10.
The list of registers to load. It must be one of:
{} encoded as D:Vd = , T = 0
{, } encoded as D:Vd = , T = 1.
Contains the base address for the access.
The alignment. It can be one of:
16 2-byte alignment, available only if is 16, encoded as a = 1.
32 4-byte alignment, available only if is 32, encoded as a = 1.
omitted Standard alignment, see Unaligned data access on page A3-5. Encoded as a = 0.
! If present, specifies writeback.
Contains an address offset applied after the access.
For more information about , !, and , see Advanced SIMD addressing mode on page A7-30.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
replicated_element = Replicate(MemU[address,ebytes], elements);
for r = 0 to regs-1
D[d+r] = replicated_element;
Exceptions
Undefined Instruction, Data Abort.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-607