ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Performance Monitors
C9.1 About the performance monitors
The basic organization of the performance monitors is:
A cycle counter. This can be programmed to increment either on every cycle, or once every 64 cycles.
A number of event counters. Each counter is configured to select the event that increments the
counter. Space is provided in the architecture for up to 31 counters. The actual number of counters is
IMPLEMENTATION DEFINED, and there is an identification mechanism for the counters.
Controls for enabling the counters, resetting the counters, flagging overflows, and enabling interrupts
on counter overflow.
The cycle counter can be enabled independently of the event counters.
The counters are held in a set of registers that can be accessed in coprocessor space. This means the counters
can be accessed from the operating system running on the processor, enabling a number of uses, including:
dynamic compilation techniques
energy management.
In addition, you can provide access to the counters from application code, if required. This enables
applications to monitor their own performance with fine grain control without requiring operating system
support. For example, an application might implement per-function performance monitoring.
There are many situations where performance monitoring features integrated into the processor are valuable
for applications and for application development. When an operating system does not use the performance
monitors itself, ARM recommends that it enables application code access to the performance monitors.
However an implementation can choose not to implement any performance monitors.
To enable interaction with external monitoring, an implementation might consider additional enhancements,
including:
Providing a set of events, from which a selection can be exported onto a bus for use as external events.
For very high frequency operation, this might introduce unacceptable timing requirements, but the
bus could be interfaced to the trace macrocell or another closely coupled resource.
Providing the ability to count external events. Here, again, there are clock frequency issues between
the processor and the system. A suitable approach might be to edge-detect changes in the signals and
to use those changes to increment a counter.
This enhancement requires the processor to implement a set of external event input pins.
Providing memory-mapped and external debug access to the performance monitor registers, to enable
the counter resources to be used for system monitoring in systems where they are not used by the
software running on the processor.
Such access is not described in this manual. Contact ARM if you require more information about this
option.
C9-2 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B