ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
The subsequent accesses to the DBGOSSRR must be either all reads or all writes. UNPREDICTABLE behavior
results if:
reads and writes are mixed
more accesses are performed than the number of registers to be saved or restored, as returned by the
first read in the OS Save sequence.
the subsequent accesses are writes, but the OS Lock is cleared with fewer writes performed than the
number of registers to be restored.
The debug logic state of the processor is unchanged if the OS Lock is cleared during or following an OS
Save sequence. The sequence is restarted the next time the OS Lock is set.
When the core power domain is powered down or when the OS Lock is not locked, reads of DBGOSSRR
return an UNKNOWN value and writes are UNPREDICTABLE.
See Example OS Save and Restore sequences on page C6-12 for software examples of the OS Save and
Restore processes.
The debug logic state preserved by the OS Save and Restore mechanism
If debug over power-down is supported, the OS Save and Restore mechanism permits the following debug
logic state to be preserved:
The registers that must be in the debug power domain, see Power domains and debug on page C6-5.
The DBGWFAR.
The DBGBVRs, DBGBCRs, DBGWVRs, DBGWCRs, and DBGVCR.
The DBGDSCCR and DBGDSMCR.
The data transfer registers DBGDTRTX and DBGDTRRX, subject to the values of
DBGDSCR.TXfull and DBGDSCR.RXfull when the OS Save sequence is performed:
— If DBGDSCR.TXfull is set to 1 then the value of DBGDTRTX is guaranteed to be saved and
restored.
— If DBGDSCR.RXfull is set to 1 then the value of DBGDTRRX is guaranteed to be saved and
restored.
— If either of these flags is not set to 1 when the OS Save sequence is performed then the value
of the corresponding register is UNKNOWN after the OS Restore sequence.
Note
The OS Save and Restore sequences must not stall reading the values of DBGDTRTX and
DBGDTRRX, and must not cause any instructions to be issued, regardless of the settings of the
DBGDSCR.ExtDCCmode access mode bits.
C6-10 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B