ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
C6.3 Debug register map
Register
number
Table C6-2 lists all of the debug registers. Full details of each register can be found in the referenced section.
The number of DBGBVR/DBGBCR and DBGWVR/DBGWCR pairs is IMPLEMENTATION DEFINED, see the
BRPs and WRPs fields of the Debug ID Register (DBGDIDR) on page C10-3. An implementation can have
up to 16 of each.
The interpretation of the information in the Access column depends on whether the coprocessor or
memory-mapped interface is used to access the register.
Collectively, registers 832-1023 are known as the management registers.
Table C6-2 Debug register map
Offset Access a Versions b Name and reference to description
0 0x000 Read-only All Debug ID Register (DBGDIDR) on page C10-3.
Not applicable c - Read-only v7 only Debug ROM Address Register (DBGDRAR) on
page C10-7.
Not applicable c - Read-only v7 only Debug Self Address Offset Register (DBGDSAR) on
page C10-8.
1-5 - - - Reserved.
6 0x018 Read/write v7 d Watchpoint Fault Address Register (DBGWFAR) on
page C10-28.
7 0x01C Read/write All Vector Catch Register (DBGVCR) on page C10-67.
8 - - - Reserved.
9 0x024 Read/write v7 only Event Catch Register (DBGECR) on page C10-78.
10 0x028 Read/write v6.1, v7 Debug State Cache Control Register (DBGDSCCR) on
page C10-81.
11 0x02C Read/write v6.1, v7 Debug State MMU Control Register (DBGDSMCR) on
page C10-84.
12-31 - - - Reserved.
32 0x080 Read/write v7 e DBGDTRRX external view f . See Host to Target Data
Transfer Register (DBGDTRRX) on page C10-40.
C6-18 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B