ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Note
Before ARMv7, the DFAR was called the Fault Address Register (FAR).
If the Security Extensions are implemented, these registers are Banked registers.
In ARMv6 variants other than ARMv6T2, the IFAR is optional.
G.7.8 c5 and c6, PMSA memory system support
The support in ARMv6 is the same as ARMv7 with the following exceptions:
ARMv6 Differences
The SCTLR.BR bit, bit [17], is not supported in ARMv6, see c1, System Control Register (SCTLR)
on page B4-45.
Bit 12 of the data and instruction fault status registers is not defined in ARMv6. See c5, Data Fault
Status Register (DFSR) on page B4-55 and c5, Instruction Fault Status Register (IFSR) on
page B4-56.
The ADFSR and the AIFSR are not defined in ARMv6. See c5, Auxiliary Data and Instruction Fault
Status Registers (ADFSR and AIFSR) on page B4-56.
Subregions are not supported. This means that DRSR[15:8] and IRSR[15:8] are not defined in
ARMv6. See c6, Data Region Size and Enable Register (DRSR) on page B4-62 and c6, Instruction
Region Size and Enable Register (IRSR) on page B4-63.
Note
Before ARMv7, the DFAR was called the Fault Address Register (FAR).
In ARMv6 variants other than ARMv6T2, the IFAR is optional.
G.7.9 c6, Watchpoint Fault Address Register (DBGWFAR)
From v6.1 of the Debug architecture, this register is also implemented as DBGWFAR in CP14, and the use
of CP15 DBGWFAR is deprecated.
In an ARMv6 implementation that includes the Security Extensions, CP15 DBGWFAR is a Secure register,
and can be accessed only from Secure privileged modes. For more information, see Restricted access CP15
registers on page B3-73.
For more information about this register see Effects of debug exceptions on CP15 registers and the
DBGWFAR on page C4-4 and Effect of entering Debug state on CP15 registers and the DBGWFAR on
page C5-4.
Table G-6 Debug fault address support
Register CRn opc1 CRm opc2
Watchpoint Fault Address Register, DBGWFAR c6 0 c0 1
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