ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.72 LDREXH
Load Register Exclusive Halfword derives an address from abase register value, loads a halfword from
memory, zero-extends it to form a 32-bit word, writes it to a register and:
if the address has the Shared Memory attribute, marks the physical address as exclusive access for
the executing processor in a shared monitor
causes the executing processor to indicate an active exclusive access in the local monitor.
For more information about support for shared memory see Synchronization and semaphores on
page A3-12. For information about memory accesses see Memory accesses on page A8-13.
Encoding T1 ARMv7
LDREXH , []
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 0 1 1 0 1 Rn Rt (1)(1)(1)(1) 0 1 0 1 (1)(1)(1)(1)
t = UInt(Rt); n = UInt(Rn);
if BadReg(t) || n == 15 then UNPREDICTABLE;
Encoding A1 ARMv6K, ARMv7
LDREXH , []
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 0 1 1 1 1 1 Rn Rt (1)(1)(1)(1) 1 0 0 1 (1)(1)(1)(1)
t = UInt(Rt); n = UInt(Rn);
if t == 15 || n == 15 then UNPREDICTABLE;
A8-148 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B