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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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See St<strong>and</strong>ard assembler syntax fields on page A8-7.<br />

Instruction Details<br />

The destination register. This register can be the SP or PC. If this register is the PC <strong>and</strong> S is<br />

specified, see SUBS PC, LR <strong>and</strong> related instructions on page B6-25.<br />

If is the PC:<br />

the instruction causes a branch to the address moved to the PC<br />

in the Thumb <strong>and</strong> ThumbEE instruction sets:<br />

— the instruction must either be outside an IT block or the last instruction of an<br />

IT block<br />

— encoding T3 is not permitted.<br />

In the Thumb <strong>and</strong> ThumbEE instruction sets, S must not be specified if is the SP. If <br />

is the SP <strong>and</strong> is the SP or PC, encoding T3 is not permitted.<br />

The source register. This register can be the SP or PC. In the Thumb <strong>and</strong> ThumbEE<br />

instruction sets, S must not be specified if is the SP or PC.<br />

Note<br />

The use of the following MOV (register) instructions is deprecated:<br />

ones in which is the SP or PC <strong>and</strong> is also the SP or PC<br />

ones in which S is specified <strong>and</strong> is the SP, is the SP, or is the PC.<br />

See also Changing between Thumb state <strong>and</strong> <strong>ARM</strong> state on page A4-2 about the use of the MOV PC,LR<br />

instruction.<br />

The pre-UAL syntax MOVS is equivalent to MOVS.<br />

Operation<br />

if ConditionPassed() then<br />

EncodingSpecificOperations();<br />

result = R[m];<br />

if d == 15 then<br />

ALUWritePC(result); // setflags is always FALSE here<br />

else<br />

R[d] = result;<br />

if setflags then<br />

APSR.N = result;<br />

APSR.Z = IsZeroBit(result);<br />

APSR.C = carry;<br />

// APSR.V unchanged<br />

Exceptions<br />

None.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. A8-197

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