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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Instruction Synchronization Barrier operation<br />

Protected Memory System <strong>Architecture</strong> (PMSA)<br />

In <strong>ARM</strong>v7, the ISB instruction is used to perform an Instruction Synchronization Barrier, see ISB on<br />

page A8-102.<br />

The deprecated CP15 c7 encoding for an Instruction Synchronization Barrier is set to 0, set to<br />

c7, set to c5, <strong>and</strong> set to 4.<br />

Data Synchronization Barrier operation<br />

In <strong>ARM</strong>v7, the DSB instruction is used to perform a Data Synchronization Barrier, see DSB on page A8-92.<br />

The deprecated CP15 c7 encoding for a Data Synchronization Barrier is set to 0, set to c7, <br />

set to c10, <strong>and</strong> set to 4. This operation performs the full system barrier performed by the DSB<br />

instruction.<br />

Data Memory Barrier operation<br />

In <strong>ARM</strong>v7, the DMB instruction is used to perform a Data Memory Barrier, see DMB on page A8-90.<br />

The deprecated CP15 c7 encoding for a Data Memory Barrier is set to 0, set to c7, set to<br />

c10, <strong>and</strong> set to 5. This operation performs the full system barrier performed by the DMB instruction.<br />

CP15 c7, No Operation (NOP)<br />

<strong>ARM</strong>v6 includes two CP15 c7 operations that are not supported in <strong>ARM</strong>v7, with encodings that become<br />

No Operation (NOP) in <strong>ARM</strong>v7. These are:<br />

The Wait For Interrupt (CP15WFI) operation. In <strong>ARM</strong>v7 this operation is performed by the WFI<br />

instruction, that is available in the <strong>ARM</strong> <strong>and</strong> Thumb instruction sets. For more information, see WFI<br />

on page A8-810.<br />

The prefetch instruction by MVA operation. In <strong>ARM</strong>v7 this operation is replaced by the PLI<br />

instruction, that is available in the <strong>ARM</strong> <strong>and</strong> Thumb instruction sets. For more information, see PLI<br />

(immediate, literal) on page A8-242, <strong>and</strong> PLI (register) on page A8-244.<br />

In <strong>ARM</strong>v7, the CP15 c7 encodings that were used for these operations must be valid write-only operations<br />

that perform a NOP. These encodings are:<br />

for the <strong>ARM</strong>v6 CP15WFI operation:<br />

— set to 0, set to c7, set to c0, <strong>and</strong> set to 4<br />

for the <strong>ARM</strong>v6 prefetch instruction by MVA operation:<br />

— set to 0, set to c7, set to c13, <strong>and</strong> set to 1.<br />

B4.6.28 CP15 c8, Not used on a PMSA implementation<br />

CP15 c8 is not used on an <strong>ARM</strong>v7-R implementation, see Unallocated CP15 encodings on page B4-27.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. B4-73

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