ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug State
A coprocessor can impose additional constraints or usage guidelines for executing coprocessor
instructions in Debug state. For example a coprocessor that signals internal exception conditions
asynchronously using the Undefined Instruction exception, as described in Undefined Instruction
exception on page B1-49, might require particular sequences of instructions to avoid the corruption
of coprocessor state associated with the exception condition.
In the case of the VFP coprocessors, these sequences are defined by the VFP subarchitecture. Other
coprocessors must define any sequences that they require.
Note
The definition of UNPREDICTABLE implies that an UNPREDICTABLE instruction executed in Debug state must
not put the processor into a state or mode in which debug is not permitted, or change the state of any register
that cannot be accessed from the current state and mode.
C5.4.1 Writing to the CPSR in Debug state
Table C5-2 lists all the instructions that normally update the CPSR, and shows their behavior in Debug state.
Which instructions are permitted in Debug state depends on the version of the Debug architecture.
Table C5-2 Instructions that modify the CPSR, and their behavior in Debug state
Instruction v6 Debug v6.1 Debug, v7 Debug
BX UNPREDICTABLE if CPSR.J is 1. Can be used
to set or clear the CPSR.T bit.
BXJ UNPREDICTABLE if either CPSR.J or CPSR.T
is 1. Can be used to set CPSR.J to 1.
UNPREDICTABLE.
UNPREDICTABLE.
SETEND UNPREDICTABLE. UNPREDICTABLE.
CPS UNPREDICTABLE. UNPREDICTABLE.
S PC,, a Can be used to set the CPSR to any value by
copying it from the SPSR of the current mode.
UNPREDICTABLE.
PC,, a Do not update the CPSR. See Data-processing instructions
with the PC as the target in Debug
state on page C5-12.
MSR CPSR_fsxc Use for setting the CPSR bits other than the
execution state bits.
MSR CPSR_ Use for setting the CPSR bits other than the
execution state bits.
Use for setting the CPSR to any
value.
UNPREDICTABLE.
LDM (exception return), RFE UNPREDICTABLE. UNPREDICTABLE.
a. is one of ADC, ADD, AND, ASR, BIC, EOR, LSL, LSR, MOV, MVN, ORR, ROR, RRX, RSB, RSC, SBC, or SUB.
C5-10 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B