ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.237 UDIV
Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value,
and writes the result to the destination register. The condition code flags are not affected.
Encoding T1 ARMv7-R
UDIV ,,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 1 1 1 0 1 1 Rn (1) (1)(1)(1) Rd 1 1 1 1 Rm
d = UInt(Rd); n = UInt(Rn); m = UInt(Rm);
if BadReg(d) || BadReg(n) || BadReg(m) then UNPREDICTABLE;
A8-468 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B