ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
LDC{2}{L} ,,[{,#+/-}] Offset. P = 1, W = 0.
LDC{2}{L} ,,[,#+/-]! Pre-indexed. P = 1, W = 1.
LDC{2}{L} ,,[],#+/- Post-indexed. P = 0, W = 1.
LDC{2}{L} ,,[], Unindexed. P =0, W =0, U =1.
where:
2 If specified, selects encoding T2 / A2. If omitted, selects encoding T1 / A1.
Instruction Details
L If specified, selects the D == 1 form of the encoding. If omitted, selects the D == 0 form.
See Standard assembler syntax fields on page A8-7. An ARM LDC2 instruction must be
unconditional.
The name of the coprocessor. The standard generic coprocessor names are p0, p1, …, p15.
The coprocessor destination register.
The base register. The SP can be used. For PC use see LDC, LDC2 (literal) on page A8-108.
+/- Is + or omitted if the immediate offset is to be added to the base register value (add == TRUE),
or – if it is to be subtracted (add == FALSE). #0 and #-0 generate different instructions.
The immediate offset used to form the address. Values are multiples of 4 in the range
0-1020. For the offset addressing syntax, can be omitted, meaning an offset of +0.
A coprocessor option. An integer in the range 0-255 enclosed in { }. Encoded in imm8.
The pre-UAL syntax LDCL is equivalent to LDCL.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
if !Coproc_Accepted(cp, ThisInstr()) then
GenerateCoprocessorException();
else
NullCheckIfThumbEE(n);
offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
address = if index then offset_addr else R[n];
repeat
Coproc_SendLoadedWord(MemA[address,4], cp, ThisInstr()); address = address + 4;
until Coproc_DoneLoading(cp, ThisInstr());
if wback then R[n] = offset_addr;
Exceptions
Undefined Instruction, Data Abort.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-107