ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
Note
Table B3-5 VMSAv7 simple access control model
AP[2] AP[1] Access a
0 0 Kernel, read/write
0 1 User, read/write
1 0 Kernel, read-only
1 1 User, read-only
a. Kernel access corresponds to access by privileged code
only.
This model depends on the definition of the AP[2] == 1, AP[1:0] == 0b11 encoding shown in Table B3-4
on page B3-28. This encoding is introduced in VMSAv7, and therefore the simplified access permissions
model cannot be supported in VMSAv6.
When the SCTLR.AFE bit is set to 1 the AP[0] bit becomes an access flag, see The access flag on
page B3-21. In this case, this simplified access permissions model becomes the only supported access
permissions model.
B3.6.2 The Execute Never (XN) attribute and instruction prefetching
An implementation must not fetch instructions from any memory location that is marked as Execute Never.
A location is marked as Execute Never when it has its XN attribute set to 1 in a Client domain. When the
MMU is enabled, instructions can only be fetched or prefetched from memory locations in Client domains
where:
XN is set to 0
valid read permissions exist
no other Prefetch Abort condition exists.
Any region of memory that is read-sensitive must be marked as Execute Never, to avoid the possibility of a
speculative prefetch accessing the memory region. For example, any memory region that corresponds to a
read-sensitive peripheral must be marked as Execute Never.
The XN attribute is not checked for domains marked as Manager. Read-sensitive memory must not be
included in domains marked as Manager, because the XN bit does not prevent prefetches in these cases.
The XN attribute is not checked when the MMU is disabled. All VMSAv7 implementations must ensure
that, when the MMU is disabled, prefetching down non-sequential paths cannot cause unwanted accesses to
read-sensitive devices.
B3-30 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B