ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
Accesses to the external views DBGDSCRext, DBGDTRRXext and DBGDTRTXext can be made through
the standard mapping of these registers, in addition to the instructions to access the internal views
DBGDSCRint, DBGDTRRXint and DBGDTRTXint provided in the Baseline CP14 interface. See Internal
and external views of the DBGDSCR and the DCC registers on page C6-21.
Features specific to v6 Debug and v6.1 Debug
Table C6-6 lists the exceptions, in the Extended CP14 interface in v6 Debug and v6.1 Debug, to the standard
mapping. All the instructions listed are UNDEFINED in ARMv6.
Table C6-6 Exceptions to the standard mapping, v6 Debug and v6.1 Debug
Register number Name Access Standard mapping, all UNDEFINED
32 Host to Target Data Transfer
Register
33 Program Counter Sampling
Register
Read/write MRC p14,0,,c0,c0,2
MCR p14,0,,c0,c0,2
Read-only MRC p14,0,,c0,c1,2
Instruction Transfer Register Write-only MCR p14,0,,c0,c1,2
34 Debug Status and Control Register Read/write MRC p14,0,,c0,c2,2
35 Target to Host Data Transfer
Register
MCR p14,0,,c0,c2,2
See also footnote e on Table C6-2 on page C6-18, regarding registers 32, 33, 34, and 35.
In v6 Debug and v6.1 Debug, no debug registers map to CP14 instructions with != 0b0000. All
instruction encodings with != 0b0000 and =0 are UNDEFINED in User mode and
UNPREDICTABLE in privileged modes. All reserved encodings with = 0b0000 are UNDEFINED in all
modes.
Table C6-7 defines an additional ARMv6 instruction for making an internal access write to the DBGDSCR.
Instruction Mnemonic Name
Read/write MRC p14,0,,c0,c3,2
MCR p14,0,,c0,c3,2
Table C6-7 Additional ARMv6 CP14 debug instruction
MCR p14,0,,c0,c1,0 DBGDSCRint Debug Status and Control Register (DBGDSCR) on page C10-10
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C6-35