ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv4 and ARMv5 Differences
For details of the CP15 c7 operations used for cleaning Write-Back caches see c7, Cache operations on
page AppxH-49.
Cache size fields
0b0101 Write-Back Format D
0b0110 c Write-Back Format A
0b0111 c Write-Back Format B
0b1110 Write-Back Format C
The Dsize and Isize fields in the CTR have the same format:
P For a VMSA implementation, indicates whether the allocation of bits [13:12] of the virtual
address is restricted, imposing the page coloring restriction. The meaning of this field is:
0 No restriction, or PMSA implementation
1 Page coloring restriction applies, see Virtual to physical translation mapping
restrictions on page AppxG-26.
Size Indicates the size of the cache, but is qualified by the M bit, see Table H-14 on
page AppxH-37.
Assoc Indicates the associativity of the cache, but is qualified by the M bit, see Cache associativity
on page AppxH-37.
M Qualifies the values in the Size and Assoc subfields.
Table H-13 Cache type values (continued)
Ctype a Cache method Cache lockdown b
a. CType values not shown are reserved and must not be used.
b. For details see c9, cache lockdown support on page AppxH-52.
c. In ARMv6 this Ctype value is reserved and must not be used.
23 22 21
11 10 9
Len Specifies the line length of the cache. The possible values of this field are:
0b00 Line length is 2 words (8 bytes)
0b01 Line length is 4 words (16 bytes)
0b10 Line length is 8 words (32 bytes)
0b11 Line length is 16 words (64 bytes).
AppxH-36 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
18
6
17
5
15
3
14
2
13
1
P 0 Size Assoc M Len
12
0