ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
This register format applies regardless of the implementation scheme for identifying the ROM Table
address.
DBGROMADDR[31:12], bits [31:12]
Bits [31:12] of the ROM Table physical address. Bits [11:0] of the address are zero.
If the Valid field, bits [1:0], is zero the value of this field is UNKNOWN.
Bits [11:2] Reserved, RAZ.
Valid, bits [1:0]
This field indicates whether the ROM Table address is valid. In the recommended
implementation it reflects the value of the DBGROMADDRV signal, and the permitted
values of this field are:
0b00 DBGROMADDRV is LOW, ROM Table address is not valid
0b11 DBGROMADDRV is HIGH, ROM Table address is valid.
Other values are reserved.
The ROM Table contains a zero-terminated list of signed 32-bit offsets from the ROM Table base to other
Memory-mapped debug components in the system. All the debug components pointed to must contain a set
of debug component identification registers compatible with the format in Debug Component Identification
Registers (DBGCID0 to DBGCID3) on page C10-102. For more information, see the ARM Debug Interface
v5 Architecture Specification.
C10.2.4 Debug Self Address Offset Register (DBGDSAR)
The Debug Self Address Offset Register, DBGDSAR, defines the offset from the ROM Table physical
address to the physical address of the debug registers for the processor.
The DBGDSAR is:
Only implemented through the Baseline CP14 interface, and therefore does not have a register
number and offset. For more information, see The CP14 debug register interfaces on page C6-32.
A read-only register.
Implemented as follows:
ARMv6 This register is not defined in ARMv6.
v7 Debug If no memory-mapped interface is provided, this register is RAZ.
Otherwise, the register gives the offset from the ROM Table physical address to the
physical address of the debug registers for the processor.
When the Security Extensions are implemented, a Common register.
It is IMPLEMENTATION DEFINED how the processor determines the value that is returned as the debug self
address offset. If the processor cannot determine the value, the Valid field in the register must be RAZ.
C10-8 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B