ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Common Memory System Architecture Features
Terms used in describing cache operations
This section describes particular terms used in the descriptions of cache maintenance operations.
Cache maintenance operations are defined to act on particular memory locations. Operations can be defined:
by the address of the memory location to be maintained, referred to as by MVA
by a mechanism that describes the location in the hardware of the cache, referred to as by set/way.
In addition, the instruction cache invalidate operation has an option that invalidates all entries in the
instruction caches.
The following subsections define the terms used to describe the cache operations:
Operations by MVA
Operations by set/way
Clean, Invalidate, and Clean and Invalidate on page B2-11.
Operations by MVA
For cache operations by MVA, these terms relate to memory addressing, and in particular the relation
between:
Modified Virtual Address (MVA)
Virtual Address (VA)
Physical Address (PA).
The term Modified Virtual Address relates to the Fast Context Switch Extension (FCSE) mechanism,
described in Appendix E Fast Context Switch Extension (FCSE). Use of the FCSE is deprecated in ARMv6
and the FCSE is optional in ARMv7. When the FCSE is absent or disabled, the MVA and VA have the same
value. However the term MVA is used throughout this section, and elsewhere in this manual, for cache and
TLB operations. This is consistent with previous issues of the ARM Architecture Reference Manual.
Virtual addresses only exist in systems with a MMU. When no MMU is implemented or the MMU is
disabled, the MVA and VA are identical to the PA.
In the cache operations, any operation described as operating by MVA includes as part of any required MVA
to PA translation:
the current system Application Space IDentifier (ASID)
the current security state, if the Security Extensions are implemented.
Operations by set/way
Cache maintenance operations by set/way refer to the particular structures in a cache. Three parameters
describe the location in a cache hierarchy that an operation works on. These parameters are:
Level The cache level of the hierarchy. The number of levels of cache is IMPLEMENTATION
DEFINED, and can be determined from the Cache Level ID Register, see:
c0, Cache Level ID Register (CLIDR) on page B3-92 for a VMSA implementation
c0, Cache Level ID Register (CLIDR) on page B4-41 for a PMSA implementation.
B2-10 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B