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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Address range<br />

Behavior of an implementation that does not include an MPU<br />

Protected Memory System <strong>Architecture</strong> (PMSA)<br />

If a PMSAv7 implementation does not include an MPU, it must adopt the default memory map behavior<br />

described in Behavior when the MPU is disabled on page B4-5.<br />

A PMSAv7 implementation that does not include an MPU is identified by an MPU Type Register entry that<br />

shows a Unified MPU with zero Data or Unified regions, see c0, MPU Type Register (MPUIR) on<br />

page B4-36.<br />

B4.1.6 Finding the minimum supported region size<br />

Table B4-2 Default memory map, showing data access attributes<br />

Data memory type<br />

Caching enabled a Caching disabled<br />

0xFFFFFFFF - 0xC0000000 Strongly-ordered Strongly-ordered<br />

0xBFFFFFFF - 0xA0000000 Shareable Device Shareable Device<br />

0x9FFFFFFF - 0x80000000 Non-shareable Device Non-shareable Device<br />

0x7FFFFFFF - 0x60000000 Normal, Shareable, Non-cacheable Normal, Shareable, Non-cacheable<br />

0x5FFFFFFF - 0x40000000 Normal, Non-shareable, Write-Through<br />

Cacheable<br />

0x3FFFFFFF - 0x00000000 Normal, Non-shareable, Write-Back,<br />

Write-Allocate Cacheable<br />

Normal, Shareable, Non-cacheable<br />

Normal, Shareable, Non-cacheable<br />

a. Caching is enabled for data accesses if the data or unified caches are enabled. See the description of the C bit in<br />

c1, System Control Register (SCTLR) on page B4-45.<br />

You can use the DRBAR to find the minimum region size supported by an implementation, by following<br />

this procedure:<br />

1. Write a valid memory region number to the RGNR. Normally you use region number 0, because this<br />

is always a valid region number.<br />

2. Write the value 0xFFFFFFFC to the DRBAR. This value sets all valid bits in the register to 1.<br />

3. Read back the value of the DRBAR. In the returned value the least significant bit set indicates the<br />

resolution of the selected region. If the least significant bit set is bit M the resolution of the region is<br />

2 M bytes.<br />

If the MPU implements separate data <strong>and</strong> instruction regions this process gives the minimum size for data<br />

regions. To find the minimum size for instruction regions, use the same procedure with the IRBAR.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. B4-7

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