ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Register Index
Register In a Description, see
Table K-1 Register index (continued)
Debug Peripheral ID Debug Peripheral Identification Registers (DBGPID0 to DBGPID4) on
page C10-98
Debug Program Counter Sampling Program Counter Sampling Register (DBGPCSR) on page C10-38
Debug ROM Address Debug ROM Address Register (DBGDRAR) on page C10-7
Debug Run Control Debug Run Control Register (DBGDRCR), v7 Debug only on
page C10-29
Debug Self Address Offset Debug Self Address Offset Register (DBGDSAR) on page C10-8
Debug State Cache Control Debug State Cache Control Register (DBGDSCCR) on page C10-81
Debug State MMU Control Debug State MMU Control Register (DBGDSMCR) on page C10-84
Debug Status and Control Debug Status and Control Register (DBGDSCR) on page C10-10
Device ID, Debug Debug Device ID Register (DBGDEVID) on page C10-6
Device Power-down and Reset Control Device Power-down and Reset Control Register (DBGPRCR), v7 Debug
only on page C10-31
Device Power-down and Reset Status Device Power-down and Reset Status Register (DBGPRSR), v7 Debug
only on page C10-34
Device Type, Debug Device Type Register (DBGDEVTYPE) on page C10-98
DFAR PMSA c6, Data Fault Address Register (DFAR) on page B4-57
VMSA c6, Data Fault Address Register (DFAR) on page B3-124
DFSR PMSA c5, Data Fault Status Register (DFSR) on page B4-55
VMSA c5, Data Fault Status Register (DFSR) on page B3-121
DMRR0-DMRR7, pre-ARMv6 c6, Memory Region registers (DMRR0-DMRR7 and IMRR0-IMRR7) on
page AppxH-47
Domain Access Control VMSA c3, Domain Access Control Register (DACR) on page B3-119
DRACR PMSA c6, Data Region Access Control Register (DRACR) on page B4-64
DRBAR PMSA c6, Data Region Base Address Register (DRBAR) on page B4-60
DRSR PMSA c6, Data Region Size and Enable Register (DRSR) on page B4-62
DTCM-NSACR, ARMv6 c9, TCM Non-Secure Access Control Registers, DTCM-NSACR and
ITCM-NSACR on page AppxG-51
AppxK-10 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B