ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

H.7 System Control coprocessor (CP15) support
ARMv4 and ARMv5 Differences
Before ARMv6, it is IMPLEMENTATION DEFINED whether a System Control coprocessor, CP15, is
implemented. However, support of ID registers, control registers, cache support, and memory management
with virtual or protected memory support resulted in the widespread adoption of a standard for control and
configuration of these features. That standard is described here. With the exception of a small number of
operations and supporting registers, for example the memory barrier operations described in c7,
Miscellaneous functions on page AppxH-51, all CP15 accesses require privileged access.
The following sections summarize the CP15 registers known to have been supported in ARMv4 or ARMv5
implementations:
Organization of CP15 registers in an ARMv4 or ARMv5 VMSA implementation on page AppxH-32
Organization of CP15 registers in an ARMv4 or ARMv5 PMSA implementation on page AppxH-33.
For details of the registers provided by a particular implementation see the appropriate Technical Reference
Manual, or other product documentation.
The rest of this section describes the ARMv4 and ARMv5 CP15 support in order of the CRn value.
Note
Definitions of CP15 registers in this appendix apply to both VMSA and PMSA implementations unless
otherwise indicated.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxH-31