ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Reset state
Debug Registers Reference
In the reset scheme described in Recommended reset scheme for v7 Debug on page C6-16, the non-debug
logic of the processor enters reset state following the assertion of at least one of:
the internal or warm reset input, nRESET
The power-up reset inputs, nCOREPORESET and nSYSPORESET.
All of these reset signals are asserted LOW.
Also, writing 1 to the Warm reset request bit of the DBGPRCR might cause the non-debug logic of the
processor to enter reset state, see Device Power-down and Reset Control Register (DBGPRCR), v7 Debug
only on page C10-31.
The processor stops executing instructions before it enters reset state.
The non-debug logic of the processor remains in reset state until:
all of the reset signals nRESET, nCOREPORESET, and nSYSPORESET, are deasserted HIGH
the Hold warm reset bit in the Device Power-down and Reset Control Register (DBGPRCR) is 0.
Note
One effect of asserting nSYSPORESET LOW is to place the debug logic into a reset state. In this state the
DBGPRSR is not accessible.
The processor then resumes execution of instructions with the Reset exception.
Powered-up state
The processor is in the powered-up state when DBGPWRDUP is HIGH, and is in the powered-down state
when DBGPWRDUP is LOW. Changing from powered-down state to powered-up state requires a reset of
the processor.
If the implementation supports separate core and debug power domains, powered-up and powered-down
state refer to the state of the core power domain.
Powered-up status is not affected by the reset state of the processor, whether that reset is:
a power-up reset, nCOREPORESET or nSYSPORESET
a warm reset, nRESET
a reset occurring because the Hold non-debug logic reset bit in the Device Power-down and Reset
Control Register (DBGPRCR) is set to 1.
For more information, see Reset and power-down support on page C6-4.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-37