ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B4.6.35 CP15 c13 Software Thread ID registers
Protected Memory System Architecture (PMSA)
The Software Thread ID registers provide locations where software can store thread identifying information,
for OS management purposes. These registers are never updated by the hardware.
The Software Thread ID registers are:
three 32-bit register read/write registers:
— User Read/Write Thread ID Register, TPIDRURW
— User Read-only Thread ID Register, TPIDRURO
— Privileged Only Thread ID Register, TPIDRPRW.
accessible in different modes:
— the User Read/Write Thread ID Register is read/write in unprivileged and privileged modes
— the User Read-only Thread ID Register is read-only in User mode, and read/write in privileged
modes
— the Privileged Only Thread ID Register is only accessible in privileged modes, and is
read/write
introduced in ARMv7.
Accessing the Software Thread ID registers
To access the Software Thread ID registers you read or write the CP15 registers with set to 0,
set to c13, set to c0, and set to:
2 for the User Read/Write Thread ID Register, TPIDRURW
3 for the User Read-only Thread ID Register, TPIDRURO
4 for the Privileged Only Thread ID Register, TPIDRPRW.
For example:
MRC p15, 0, , c13, c0, 2 ; Read CP15 User Read/Write Thread ID Register
MCR p15, 0, , c13, c0, 2 ; Write CP15 User Read/Write Thread ID Register
MRC p15, 0, , c13, c0, 3 ; Read CP15 User Read-only Thread ID Register
MCR p15, 0, , c13, c0, 3 ; Write CP15 User Read-only Thread ID Register
MRC p15, 0, , c13, c0, 4 ; Read CP15 Privileged Only Thread ID Register
MCR p15, 0, , c13, c0, 4 ; Write CP15 Privileged Only Thread ID Register
B4.6.36 CP15 c14, Not used
CP15 c14 is not used on any ARMv7 implementation, see Unallocated CP15 encodings on page B4-27.
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