ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.181 SMUSD
Signed Dual Multiply Subtract performs two signed 16 × 16-bit multiplications. It subtracts one of the
products from the other, and writes the result to the destination register.
Optionally, you can exchange the halfwords of the second operand before performing the arithmetic. This
produces top × bottom and bottom × top multiplication.
Overflow cannot occur.
Encoding T1 ARMv6T2, ARMv7
SMUSD{X} ,,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 1 1 0 1 0 0 Rn 1 1 1 1 Rd 0 0 0 M Rm
d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); m_swap = (M == ‘1’);
if BadReg(d) || BadReg(n) || BadReg(m) then UNPREDICTABLE;
Encoding A1 ARMv6*, ARMv7
SMUSD{X} ,,
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 1 1 1 0 0 0 0 Rd 1 1 1 1 Rm 0 1 M 1 Rn
d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); m_swap = (M == ‘1’);
if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
A8-360 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B