ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.349 VPADD (integer)
Vector Pairwise Add (integer) adds adjacent pairs of elements of two vectors, and places the results in the
destination vector.
The operands and result are doubleword vectors.
The operand and result elements must all be the same type, and can be 8-bit, 16-bit, or 32-bit integers. There
is no distinction between signed and unsigned integers.
Figure A8-3 shows an example of the operation of VPADD.
Encoding T1 / A1 Advanced SIMD
VPADD. , ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 1 0 D size Vn Vd 1 0 1 1 N Q M 1 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 0 0 D size Vn Vd 1 0 1 1 N Q M 1 Vm
if size == ‘11’ || Q == ‘1’ then UNDEFINED;
esize = 8