ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VCGT. {,} , Encoded as Q = 1
VCGT. {,} , Encoded as Q = 0
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VCGT instruction must
be unconditional.
The data types for the elements of the operands. It must be one of:
S8 encoding T1 / A1, size = 0b00, U = 0
S16 encoding T1 / A1, size = 0b01, U = 0
S32 encoding T1 / A1, size = 0b10, U = 0
U8 encoding T1 / A1, size = 0b00, U = 1
U16 encoding T1 / A1, size = 0b01, U = 1
U32 encoding T1 / A1, size = 0b10, U = 1
F32 encoding T2 / A2, sz = 0.
, , The destination vector and the operand vectors, for a quadword operation.
, , The destination vector and the operand vectors, for a doubleword operation.
Operation
enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp};
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
op1 = Elem[D[n+r],e,esize]; op2 = Elem[D[m+r],e,esize];
case type of
when VCGTtype_signed test_passed = (SInt(op1) > SInt(op2));
when VCGTtype_unsigned test_passed = (UInt(op1) > UInt(op2));
when VCGTtype_fp test_passed = FPCompareGT(op1, op2, FALSE);
Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);
Exceptions
Undefined Instruction.
Floating-point exceptions: Input Denormal and Invalid Operation.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-561