ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VQSHL{U}. {,} , # Encoded as Q = 1
VQSHL{U}. {,} , # Encoded as Q = 0
where:
Instruction Details
U If present, specifies that the results are unsigned, although the operands are signed.
See Standard assembler syntax fields on page A8-7. An ARM VQSHL or VQSHLU instruction
must be unconditional.
The data type for the elements of the vectors. It must be one of:
S encoded as:
U = 0, op = 1, if U is absent
U = 1, op = 0, if U is present
U encoded as U = 1, op = 1. Not available for VQSHLU.
The data size for the elements of the vectors. It must be one of:
8 Encoded as L = ’0’, imm6 = ’001’. is encoded in imm6.
16 Encoded as L = ’0’, imm6 = ’01’. is encoded in imm6.
32 Encoded as L = ’0’, imm6 = ’1’. is encoded in imm6.
64 Encoded as L = ’1’. is encoded in imm6.
, The destination vector, and the operand vector, for a quadword operation.
, The destination vector, and the operand vector, for a doubleword operation.
The immediate value, in the range 0 to -1. See the description of for how
is encoded.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
operand = Int(Elem[D[m+r],e,esize], src_unsigned);
(result, sat) = SatQ(operand