ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Unpriv_instrs, bits [3:0]
The CPUID Identification Scheme
Indicates the supported Unprivileged instructions. Permitted values are:
0b0000 None supported. No T variant instructions are implemented.
0b0001 Adds support for LDRBT, LDRT, STRBT, and STRT instructions.
0b0010 As for 0b0001, and adds support for LDRHT, LDRSBT, LDRSHT, and STRHT
instructions.
c0, Instruction Set Attribute Register 5 (ID_ISAR5)
The format of the ID_ISAR5 is:
31 0
Bits [31:0] Reserved, RAZ.
Accessing the Instruction Set Attribute registers
To access the Instruction Set Attribute Registers you read the CP15 registers with set to 0, set
to c0, set to c2, and set to:
0 for the ID_ISAR0
1 for the ID_ISAR1
2 for the ID_ISAR2
3 for the ID_ISAR3
4 for the ID_ISAR4
5 for the ID_ISAR5.
For example:
Reserved, RAZ
MRC p15, 0, , c0, c2, 3 ; Read Instruction Set Attribute Register 3
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B5-33