ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Instruction Set Encoding
A5.2.3 Data-processing (immediate)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 1 op Rn
If op == 0b10xx0, see Data-processing and miscellaneous instructions on page A5-4.
Table A5-5 shows the allocation of encodings in this space. These encodings are in all architecture variants.
op Rn Instruction See
Table A5-5 Data-processing (immediate) instructions
0000x - Bitwise AND AND (immediate) on page A8-34
0001x - Bitwise Exclusive OR EOR (immediate) on page A8-94
0010x not 1111 Subtract SUB (immediate, ARM) on page A8-420
1111 Form PC-relative address ADR on page A8-32
0011x - Reverse Subtract RSB (immediate) on page A8-284
0100x not 1111 Add ADD (immediate, ARM) on page A8-22
1111 Form PC-relative address ADR on page A8-32
0101x - Add with Carry ADC (immediate) on page A8-14
0110x - Subtract with Carry SBC (immediate) on page A8-302
0111x - Reverse Subtract with Carry RSC (immediate) on page A8-290
10001 - Test TST (immediate) on page A8-454
10011 - Test Equivalence TEQ (immediate) on page A8-448
10101 - Compare CMP (immediate) on page A8-80
10111 - Compare Negative CMN (immediate) on page A8-74
1100x - Bitwise OR ORR (immediate) on page A8-228
1101x - Move MOV (immediate) on page A8-194
1110x - Bitwise Bit Clear BIC (immediate) on page A8-50
1111x - Bitwise NOT MVN (immediate) on page A8-214
These instructions all have modified immediate constants, rather than a simple 12-bit binary number. This
provides a more useful range of values. For details see Modified immediate constants in ARM instructions
on page A5-9.
A5-8 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B