ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
When floating-point operation is disabled because FPEXC.EN is 0, all Advanced SIMD and VFP
instructions are treated as Undefined Instructions except for:
a VMSR to the FPEXC or FPSID register
a VMRS from the FPEXC, FPSID, MVFR0, or MVFR1 register.
These instructions can be executed only in privileged modes.
Note
When FPEXC.EN == 0, these operations are treated as Undefined Instructions:
— a VMSR to the FPSCR
— a VMRS from the FPSCR
If a VFP implementation contains system registers additional to the FPSID, FPSCR, FPEXC,
MVFR0, and MVFR1 registers, the behavior of VMSR instructions to them and VMRS instructions from
them is SUBARCHITECTURE DEFINED.
Pseudocode details of enabling the Advanced SIMD and VFP extensions
The following pseudocode takes appropriate action if an Advanced SIMD or VFP instruction is used when
the extensions are not enabled:
// CheckAdvSIMDOrVFPEnabled()
// ==========================
CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)
if HaveSecurityExt() then
// Check Non-secure Access Control Register for permission to use CP10/11.
if NSACR.cp10 != NSACR.cp11 then UNPREDICTABLE;
if SCR.NS == ‘1’ && NSACR.cp10 == ‘0’ then UNDEFINED;
// Check Coprocessor Access Control Register for permission to use CP10/11.
if CPACR.cp10 != CPACR.cp11 then UNPREDICTABLE;
case CPACR.cp10 of
when ‘00’ UNDEFINED;
when ‘01’ if !CurrentModeIsPrivileged() then UNDEFINED; // else CPACR permits access
when ‘10’ UNPREDICTABLE;
when ‘11’ // CPACR permits access
// If the Advanced SIMD extension is specified, check whether it is disabled.
if advsimd && CPACR.ASEDIS == ‘1’ then UNDEFINED;
// If required, check FPEXC enabled bit.
if include_fpexc_check && FPEXC.EN == ‘0’ then UNDEFINED;
return;
// CheckAdvSIMDEnabled()
// =====================
CheckAdvSIMDEnabled()
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