ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Register Index
Register In a Description, see
PMINTENCLR c9, Interrupt Enable Clear Register (PMINTENCLR) on page C10-119
PMINTENSET c9, Interrupt Enable Set Register (PMINTENSET) on page C10-118
PMOVSR c9, Overflow Flag Status Register (PMOVSR) on page C10-110
PMSELR c9, Event Counter Selection Register (PMSELR) on page C10-113
PMSWINC c9, Software Increment Register (PMSWINC) on page C10-112
PMUSERENR c9, User Enable Register (PMUSERENR) on page C10-117
PMXEVCNTR c9, Event Count Register (PMXEVCNTR) on page C10-116
PMXEVTYPER c9, Event Type Select Register (PMXEVTYPER) on page C10-115
Power-down and Reset Control Device Power-down and Reset Control Register (DBGPRCR), v7 Debug
only on page C10-31
Power-down and Reset Status Device Power-down and Reset Status Register (DBGPRSR), v7 Debug
only on page C10-34
Prefetch Status, ARMv6 c7, Block Transfer Status Register on page AppxG-43
Primary Region Remap VMSA c10, Primary Region Remap Register (PRRR) on page B3-143
Processor Feature CP15 c0, Processor Feature registers on page B5-4
Program Counter Sampling, Debug Program Counter Sampling Register (DBGPCSR) on page C10-38
PRRR VMSA c10, Primary Region Remap Register (PRRR) on page B3-143
PSR Program Status Registers (PSRs) on page B1-14
Q0 - Q15 Advanced SIMD and VFP extension registers on page A2-21
R0 - R15 ARM core registers on page A2-11 for application-level description
ARM core registers on page B1-9 for system-level description
R0_usr - R12_usr ARM core registers on page B1-9
R8_fiq - R12_fiq ARM core registers on page B1-9
Table K-1 Register index (continued)
RGNR PMSA c6, MPU Region Number Register (RGNR) on page B4-66
Run Control, Debug Debug Run Control Register (DBGDRCR), v7 Debug only on
page C10-29
S0 - S31 Advanced SIMD and VFP extension registers on page A2-21
AppxK-18 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B