ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
In both cases, the behavior in earlier architecture versions is a branch that remains in the same
instruction set state. For more information, see:
— Interworking on page AppxG-4, for ARMv6
— Interworking on page AppxH-5, for ARMv5 and ARMv4.
Pseudocode details of ARM core register operations
The following pseudocode gives access to the general-purpose registers:
// The names of the banked core registers.
enumeration RName {RName_0usr, RName_1usr, RName_2usr, RName_3usr, RName_4usr, RName_5usr,
RName_6usr, RName_7usr, RName_8usr, RName_8fiq, RName_9usr, RName_9fiq,
RName_10usr, RName_10fiq, RName_11usr, RName_11fiq, RName_12usr, RName_12fiq,
RName_SPusr, RName_SPfiq, RName_SPirq, RName_SPsvc,
RName_SPabt, RName_SPund, RName_SPmon,
RName_LRusr, RName_LRfiq, RName_LRirq, RName_LRsvc,
RName_LRabt, RName_LRund, RName_LRmon,
RName_PC};
// The physical array of banked core registers.
//
// _R[RName_PC] is defined to be the address of the current instruction. The
// offset of 4 or 8 bytes is applied to it by the register access functions.
array bits(32) _R[RName];
// RBankSelect()
// =============
RName RBankSelect(bits(5) mode, RName usr, RName fiq, RName irq,
RName svc, RName abt, RName und, RName mon)
if BadMode(mode) then
UNPREDICTABLE;
else
case mode of
when ‘10000’ result = usr; // User mode
when ‘10001’ result = fiq; // FIQ mode
when ‘10010’ result = irq; // IRQ mode
when ‘10011’ result = svc; // Supervisor mode
when ‘10110’ result = mon; // Monitor mode
when ‘10111’ result = abt; // Abort mode
when ‘11011’ result = und; // Undefined mode
when ‘11111’ result = usr; // System mode uses User mode registers
return result;
// RfiqBankSelect()
// ================
RName RfiqBankSelect(bits(5) mode, RName usr, RName fiq)
return RBankSelect(mode, usr, fiq, usr, usr, usr, usr, usr);
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