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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Instruction Details<br />

A8.6.217 SUBS PC, LR <strong>and</strong> related instructions<br />

These instructions are for system level use only. See SUBS PC, LR <strong>and</strong> related instructions on page B6-25.<br />

A8.6.218 SVC (previously SWI)<br />

Supervisor Call, previously called a Software Interrupt. For more information, see Exceptions on<br />

page B1-30, <strong>and</strong> in particular Supervisor Call (SVC) exception on page B1-52.<br />

You can use this instruction as a call to an operating system to provide a service.<br />

Encoding T1 <strong>ARM</strong>v4T, <strong>ARM</strong>v5T*, <strong>ARM</strong>v6*, <strong>ARM</strong>v7<br />

SVC #<br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 0 1 1 1 1 1 imm8<br />

imm32 = ZeroExtend(imm8, 32);<br />

// imm32 is for assembly/disassembly, <strong>and</strong> is ignored by hardware. SVC h<strong>and</strong>lers in some<br />

// systems interpret imm8 in software, for example to determine the required service.<br />

Encoding A1 <strong>ARM</strong>v4*, <strong>ARM</strong>v5T*, <strong>ARM</strong>v6*, <strong>ARM</strong>v7<br />

SVC #<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

cond 1 1 1 1 imm24<br />

imm32 = ZeroExtend(imm24, 32);<br />

// imm32 is for assembly/disassembly, <strong>and</strong> is ignored by hardware. SVC h<strong>and</strong>lers in some<br />

// systems interpret imm24 in software, for example to determine the required service.<br />

A8-430 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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