ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
B1.6 Exceptions
An exception causes the processor to suspend program execution to handle an event, such as an externally
generated interrupt or an attempt to execute an undefined instruction. Exceptions can be generated by
internal and external sources.
Normally, when an exception is taken the processor state is preserved immediately, before handling the
exception. This means that, when the event has been handled, the original state can be restored and program
execution resumed from the point where the exception was taken.
More than one exception might be generated at the same time, and a new exception can be generated while
the processor is handling an exception.
The following sections describe exception handling in general:
Exception vectors and the exception base address
Exception priority order on page B1-33
Exception entry on page B1-34
Exception return on page B1-38
Exception-handling instructions on page B1-41
Control of exception handling by the Security Extensions on page B1-41
Low interrupt latency configuration on page B1-43.
Wait For Event and Send Event on page B1-44
Wait For Interrupt on page B1-47.
The following sections give details of each exception:
Reset on page B1-48
Undefined Instruction exception on page B1-49
Supervisor Call (SVC) exception on page B1-52
Secure Monitor Call (SMC) exception on page B1-53
Prefetch Abort exception on page B1-54
Data Abort exception on page B1-55
IRQ exception on page B1-58
FIQ exception on page B1-60.
B1.6.1 Exception vectors and the exception base address
When an exception is taken, processor execution is forced to an address that corresponds to the type of
exception. These addresses are called the exception vectors.
By default, the exception vectors are eight consecutive word-aligned memory addresses, starting at an
exception base address. Table B1-3 on page B1-31 shows the assignment of the exceptions to the eight
memory addresses.
B1-30 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B