ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Performance Monitors
C9.8 CP15 c9 register map
The performance monitor registers are mapped into part of the CP15 register map. The registers are
described in Performance monitor registers on page C10-105.
Figure C9-1 shows the CP15 c9 encodings for the recommended performance monitor registers, and the
reserved encodings for IMPLEMENTATION DEFINED performance monitors:
CRn opc1 CRm opc2
c9 0 c12 0
1
2
3
4
5
c13 0
1
2
c14
0
1
2
PMCR, Performance Monitor Control Register
PMCNTENSET, Count Enable Set Register
PMCNTENCLR, Count Enable Clear Register
PMOVSR, Overflow Flag Status Register
PMSWINC, Software Increment Register
PMSELR, Event Counter Selection Register
PMCCNTR, Cycle Count Register
PMXEVTYPER, Event Type Select Register
PMXEVCNTR, Event Count Register
PMUSERENR, User Enable Register
PMINTENSET, Interrupt Enable Set Register
PMINTENCLR, Interrupt Enable Clear Register
c15 {0-7} ‡ Reserved for IMPLEMENTATION DEFINED performance monitors
Read-only Read/Write
Write-only
‡ Access depends on the operation
Figure C9-1 Recommended CP15 performance monitor registers
Table C9-1 lists the instructions used to access the recommended performance monitor registers.
Instruction a Description or notes
MRC p15,0,,c9,c12,0
MCR p15,0,,c9,c12,0
MRC p15,0,,c9,c12,1
MCR p15,0,,c9,c12,1
MRC p15,0,,c9,c12,2
MCR p15,0,,c9,c12,2
MRC p15,0,,c9,c12,3
MCR p15,0,,c9,c12,3
Table C9-1 Recommended performance monitor registers
c9, Performance Monitor Control Register (PMCR) on page C10-105.
c9, Count Enable Set Register (PMCNTENSET) on page C10-108.
c9, Count Enable Clear Register (PMCNTENCLR) on page C10-109.
c9, Overflow Flag Status Register (PMOVSR) on page C10-110.
C9-10 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B