ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Register number Access a
Debug Registers Reference
Table C10-20 Processor identification registers
Mnemonic Register
832 Read-only MIDR Main ID Register b
833 Read-only CTR Cache Type Register b
834 Read-only TCMTR TCM Type Register b
835 Read-only TLBTR TLB Type Register b
836 Read-only MPUIR MPU Type Register b
837 Read-only MPIDR Multiprocessor Affinity Register b
838, 839 Read-only - Alias of Main ID Register b
840 Read-only ID_PFR0 Processor Feature Register 0
841 Read-only ID_PFR1 Processor Feature Register 1
842 Read-only ID_DFR0 Debug Feature Register 0
843 Read-only ID_AFR0 Auxiliary Feature Register 0
844 Read-only ID_MMFR0 Memory Model Feature Register 0
845 Read-only ID_MMFR1 Memory Model Feature Register 1
846 Read-only ID_MMFR2 Memory Model Feature Register 2
847 Read-only ID_MMFR3 Memory Model Feature Register 3
848 Read-only ID_ISAR0 Instruction Set Attribute Register 0
849 Read-only ID_ISAR1 Instruction Set Attribute Register 1
850 Read-only ID_ISAR2 Instruction Set Attribute Register 2
851 Read-only ID_ISAR3 Instruction Set Attribute Register 3
852 Read-only ID_ISAR4 Instruction Set Attribute Register 4
853 Read-only ID_ISAR5 Instruction Set Attribute Register 5
854-895 - - Reserved, UNK/SBZP
a. For more information, see CP14 debug registers access permissions on page C6-36 and
Permission summaries for memory-mapped and external debug interfaces on page C6-45.
b. Identification registers with register numbers 832-839 return the same value as an MRC
instruction MRC p15,0,,c0,c0,, where = (register number - 832).
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-89