ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
VMSAv6 translation table format
The VMSAv6 translation table format is fully compatible with the virtual memory support in ARMv7-A. It
includes the following features:
the ability to mark a virtual address as either global or context-specific
the ability to encode the Normal, Device, or Strongly-ordered memory type into the translation tables
the Shareable attribute
the XN execute never access permission attribute
a third AP bit
a TEX bitfield used with the C and B bits to define the cache attributes for each page of memory
support for an application specific (ASID) or global identifier
16MB Supersections, and the ability to map a Supersection to a 16MB range.
Related to this new translation table format, VMSAv6 provides:
support for two translation table base registers and an associated control register
independent fault status and fault address registers for reporting Prefetch Abort exceptions and Data
Abort exceptions
a Context ID Register, CONTEXTIDR.
ARMv6K added the following features to VMSAv6:
An additional access permission encoding, AP[2:0] == 0b111, and an associated simplified access
permissions model. See Access permissions on page B3-28, and Simplified access permissions model
on page B3-29.
The access flag feature. See The access flag on page B3-21.
TEX remapping. See Memory region attribute descriptions when TEX remap is enabled on
page B3-34.
Virtual to physical translation mapping restrictions
An ARMv6 implementation can restrict the mapping of pages that remap virtual address bits [13:12]. This
restriction, called page coloring, supports the handling of aliases by an implementation that uses VIPT
caches. On an implementation that imposes this restriction, the most significant bit of the cache size fields
for the instruction and data caches in the CTR is Read-As-One, see c0, Cache Type Register (CTR) on
page AppxH-35.
To avoid alias problems, this restriction enables these bits of the virtual address to be used to index into the
cache without requiring hardware support. The restriction supports virtual indexing on caches where a cache
way has a maximum size of 16KB. There is no restriction on the number of ways supported. Cache ways of
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