ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.328 VMOV (ARM core register to scalar)
This instruction copies a byte, halfword, or word from an ARM core register into an Advanced SIMD scalar.
On a VFP-only system, this instruction transfers one word to the upper or lower half of a double-precision
floating-point register from an ARM core register. This is an identical operation to the Advanced SIMD
single word transfer.
For more information about scalars see Advanced SIMD scalars on page A7-9.
Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD if opc1 == ’0x’ && opc2 == '00'
Advanced SIMD otherwise
VMOV. ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 0 0 opc1 0 Vd Rt 1 0 1 1 D opc2 1 (0)(0)(0)(0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 1 0 0 opc1 0 Vd Rt 1 0 1 1 D opc2 1 (0)(0)(0)(0)
case opc1:opc2 of
when ‘1xxx’ advsimd = TRUE; esize = 8; index = UInt(opc1:opc2);
when ‘0xx1’ advsimd = TRUE; esize = 16; index = UInt(opc1:opc2);
when ‘0x00’ advsimd = FALSE; esize = 32; index = UInt(opc1);
when ‘0x10’ UNDEFINED;
d = UInt(D:Vd); t = UInt(Rt);
if t == 15 || (CurrentInstrSet() != InstrSet_ARM && t == 13) then UNPREDICTABLE;
A8-644 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B